1. Field of the Invention
The present invention relates to bus interfaces, and more particularly to reducing switching noise in a bus interface to a large bit-width bus.
2. Description of the Related Art
As communication buses carrying data and electronic signals are designed to accommodate an increasing number of bits, the problem of electronic switching noise substantially increases in severity. For example, an implementation of an Asynchronous Transfer Mode (ATM) packet routing system may be designed to accommodate an entire 53-byte standard packet as a single 424-bit (53xc3x978) wide data word. Unfortunately, the combined electronic switching noise resulting from the in-phase switching of four hundred or more bits of a wide data bus must be addressed for this implementation, typically at a large cost in circuit resources.
A data bus for communicating a data word includes a respective bus line for carrying each respective bit within the data word. Each of the bus lines has two states, representing two possible binary values of each respective bit. Electronic switching noise is created when a bus line switches from a first state to a second state, which corresponds to a bit carried on the bus line changing from one logic state to the other logic state. A worst case switching noise condition occurs when all bits in a large-width multiple-bit data word switch at the same time in the same direction (for instance, from all xe2x80x9c1xe2x80x9ds to all xe2x80x9c0xe2x80x9ds). The amount of switching noise increases in approximately a linear manner from an essentially zero noise condition in which no bits switch to the worst case switching condition when all the bits switch.
Data transitions in which a large number of bits switch occur infrequently. However, the bus interface circuit must be designed to withstand the very large power supply spikes that result when worst-case sequences of data words are communicated on the bus. Typically, a large power supply voltage spike results when a large number of bits of a data bus are changed in the same direction simultaneously. Thus, when the electronic switching noise becomes sufficiently large, a device connected to the bus may switch logical state unintentionally so that incorrect data is communicated via the bus.
What is needed is a bus interface circuit that reduces worst case switching noise so that potential data transmission errors are reduced.
In accordance with the present invention, within a data word carried on a bus the maximum number of bits that simultaneously switch states is reduced by one-half, thereby approximately halving the worst case electronic switching noise spike that effects the system power supply or ground reference.
In accordance with the present invention, a method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line. An indicator signal is provided to the bus to indicate which polarity form of the data word is driven onto the bus. The data word includes a plurality of bits and the bus includes a corresponding plurality of bus lines for carrying the plurality of bits. Each of the plurality of bus lines has a first and a second state representing binary values of a bit associated therewith. The method may also include receiving the data word from the bus, receiving the indicator signal from the bus, and conditionally inverting the polarity form of the data word in response to the indicator signal.
The first and second states may be first and second voltages or may be first and second currents. The first and second states of each respective bus line may represent respective first and second binary values of an associated bit when the indicator signal is provided in a first state, and respective second and first binary values of an associated bit when the indicator signal is provided in a second state. The data word and a present data word corresponding to the present state of each bus line may be driven onto the bus by a single bus interface or by different bus interfaces. The invention lends itself well to implementation within a bus interface of an integrated circuit, which circuit may be used with other circuits to form a system carrying out the invention over a system bus. The bus may be either bidirectional or unidirectional, and may include circuits which both send and receive data words onto or from the bus.
In one embodiment of the invention, a bus interface for communicating a data word via a bus includes means for driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and means for providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus.
In another embodiment of the invention, a method of communicating a data word via a bus includes the steps of: (1) comparing a present data word on the bus (i.e., present bus state) with a next data word to be next communicated via the bus; (2) driving the next data word onto the bus when fewer than a certain number of bits within the next data word differ from corresponding bits within the present data word; (3) driving an inverted next data word onto the bus when at least the certain number of bits within the next data word differ from corresponding bits within the present data word; and (4) driving an indicator signal onto the bus to indicate whether an inverted next data word is driven onto the bus. The certain number of bits may be chosen to be one-half the number of bits forming the data word, approximately one-half the number of bits forming the data word, or another number of bits.
In yet another embodiment, a bus interface circuit for communicating a data word via a bus, the data word including a plurality of bits, the bus including a corresponding plurality of individual bus lines for carrying the plurality of bits, each of the plurality of bus lines having first and second states representing binary values of a bit associated therewith, the bus interface includes a sending circuit which includes: (1) a determining circuit, responsive to a present data word on the bus and a data word to be next communicated onto the bus, for determining whichever one of the next data word and a complement next data word, if driven onto the bus, requires fewer bus lines to change state relative to the present data word on the bus; and (2) a polarity circuit for driving the next data word or the complement next data word onto the bus as determined by the determining circuit.
The polarity circuit may include a circuit for conditionally inverting each bit of the next data word to form the complement next data word. Alternatively, the polarity circuit may include a multiplexer circuit for choosing between the data word and the complement next data word, or may include other circuits. The determining circuit may be (but need not be) spatially distributed, having a respective portion thereof in close proximity with a respective output circuit for each respective bit of the data word. Likewise, the polarity circuit may be spatially distributed, having a respective portion thereof in close proximity with a respective output circuit for each respective bit of the data word. The bus interface may also include a receiving circuit for receiving a data word from the bus, and for reforming a data word upon receiving a complement data word from the bus.
The determining circuit may include: (1) a comparison circuit for determining, for each bit of data word to be next communicated onto the bus, whether each bit of the next data word differs from a corresponding bit of the present data word on the bus; and (2) a tally circuit coupled to the comparison circuit for determining whether at least a certain number of bits within the next data word differ from corresponding bits within the present data word.
One embodiment of the tally circuit includes: (1) a digital adder circuit for determining a total number of bits within the next data word which differ from respective bits within the present data word; (2) a reference circuit for generating a reference digital number; and (3) a numerical comparator circuit for comparing the total number of bits which differ against the reference digital number, and for generating a POLARITY_CONTROL signal accordingly. The POLARITY_CONTROL signal may be an INVERT signal. Another embodiment of the tally circuit includes: (1) a summing node for accumulating an incremental signal for each bit within the next data word which differs from a corresponding bit within the present data word; and (2) a differential comparator having a first input terminal coupled to the summing node, having a second input terminal, and having an output terminal coupled to a POLARITY_CONTROL signal line. Yet another embodiment of the tally circuit includes: (1) a first summing node for accumulating an incremental signal for each bit of a first portion of bits within the next data word which differs from a corresponding bit within the present data word; (2) a second summing node for accumulating an incremental signal for each bit of a remaining portion of bits other than the first portion of bits within the next data word which matches a corresponding bit within the present data word; and (3) a differential comparator having a first input terminal coupled to the first summing node, having a second input terminal coupled to the second summing node, and having an output terminal coupled to a POLARITY_CONTROL signal line.
Many advantages are gained by the present invention. One advantage is that worst-case switching noise is reduced. Another advantage is that switching noise is reduced using a noise reduction circuit that is simple, small and fast so that transmission delay is not significantly impeded (and bandwidth, of course, need not be impacted at all). Another advantage is that fewer power (e.g., VDD) and reference (e.g., VSS or GND) pins need be employed to drive binary signals onto the bus. In particular, for the same amount of switching noise the number of power and reference pins is approximately halved by the described circuits and operating method. It is also highly advantageous that, since fewer pins are utilized in an integrated circuit, the cost of manufacturing the integrated circuit package is substantially reduced. Still another advantage is that power is conserved by reducing the number of bits switched at one time from possibly many bits to substantially fewer bits. In particular, the dynamic power for driving signals onto the bus is reduced.
The invention may be advantageously implemented using a spatially distributed analog circuit. Such an analog implementation may be much smaller than a digital implementation, particularly for data buses with many bits.